1. Field of the Invention
The present invention relates to power supply circuits and liquid crystal display devices. More particularly, the present invention relates to a power supply circuit arranged to generate an intermediate voltage and a liquid crystal display device operating according to an output of the power supply circuit.
2. Description of the Background Art
The arrangement of a conventional liquid crystal display device will be described with reference to FIG. 11. A liquid crystal display device 4000 shown in FIG. 11 includes a liquid crystal panel 4500 having pixels arranged in a matrix, a Y driver 4100 to drive the pixels of liquid crystal panel 4500 in the horizontal axis direction, an X driver 4200 to drive the pixels of liquid crystal panel 4500 in the vertical axis direction, a control circuit 4300 to control Y driver 4100 and X driver 4200, and a power supply circuit 4400 to supply Y driver 4100 and X driver 4200 with a reference power supply voltage for driving.
One example of the power supply circuit will be described with reference to FIG. 12. A power supply circuit 900 shown in FIG. 12 outputs reference power supply voltages through resistor division. Power supply circuit 900 includes resistors R1, R2, . . . , Rn which are connected in series between a node supplied with a power supplied voltage VEE and a node supplied with a ground voltage GND. Power supply circuit 900 is formed to divide a difference in voltage between power supply voltage VEE and ground voltage GND by bleeder resistors R1 to Rn and thereby obtain reference power supply voltages (intermediate voltages) V0 to V4, for example.
Another example of the conventional power supply circuit is as shown in FIG. 13. A power supply circuit 910 shown in FIG. 13 includes bleeder resistors R1 to Rn which are connected in series between a node supplied with power supply voltage VEE and a node supplied with ground voltage GND, and operational amplifiers OA0, OA1, . . . , OA4. Operational amplifiers OA0, OA1, . . . , OA4 are generically referred to as operational amplifiers OA.
Power supply circuit 910 divides a voltage which corresponds to a difference between power supply voltage VEE and ground voltage GND by using the resistors, performs impedance conversion through operational amplifiers OA to stabilize each intermediate voltage, and then outputs the intermediate voltages.
Operational amplifier OA includes transistors Q91, Q92, Q93, Q94 and Q95 as shown in FIG. 14. Transistors Q91, Q92 and Q95 are PMOS transistors while transistors Q93 and Q94 are NMOS transistors.
The gate of transistor Q91 is connected to an inversion input terminal N (corresponding to symbol "-" in FIG. 13), and the gate of transistor Q92 is connected to a non-inversion input terminal P (corresponding to symbol "+" in FIG. 13).
Transistors Q93 and Q94 have their sources receiving ground voltage GND. Transistor Q95 has its gate connected to a bias input terminal BIAS and supplied with a bias voltage. Transistor Q95 has its source receiving power supply voltage VEE and its drain connected commonly to the sources of transistors Q91 and Q92. Transistor Q95 serves as a constant current source to supply transistors Q91 and Q92 a suitable bias current.
Operational amplifier OA further includes transistors Q96 and Q97 and a capacitance element C0. Transistor Q97 is an NMOS transistor while transistor Q96 is a PMOS transistor. Transistor Q97 has its gate connected to the drain of transistor Q94, its source receiving the ground voltage, and its drain connected to an output terminal OUT.
Transistor Q96 is connected between a node supplied with power supply voltage VEE and output terminal OUT and has its gate supplied with the bias voltage from bias input terminal BIAS. Transistor Q96 operates as a constant current source load.
Capacitance element C0 is connected between the drain and the gate of transistor Q97.
In a liquid crystal display device, a larger number of pixels increases load capacitance, and higher impedance of a power supply for driving the liquid crystal causes a noise on a liquid crystal output waveform. When power supply circuit Q910 is used, degradation in the display quality can be prevented from dropping by attaining lower impedance through operational amplifiers OA.
In any of such conventional power supply circuits, the resistance value of a bleeder resistor is desirably smaller to stabilize a reference power supply voltage. However, a smaller resistance value of the bleeder resistor results in power consumption increase of the power supply circuit.
In power supply circuit Q910, if a sufficient power amount is to be obtained for liquid crystal display by using an operational amplifier, the current flowing in a constant current circuit in the operational amplifier has to be made higher to some extent. That substantially prevents lower power consumption.
In order to cope with the problem, Japanese Patent Laying-Open No. 55-146487 (hereinafter, referred to as Document 1) discloses a power supply circuit which can stabilize an output voltage even if the resistance value of a bleeder resistor is made higher.
The power supply circuit arrangement shown in Document 1 will be described with reference to FIG. 15. A power supply circuit 920 shown in FIG. 15 obtains intermediate voltages using higher resistance and detects voltage fluctuation which exceeds an acceptable value to suppress the fluctuation using MOS transistors.
Power supply circuit 920 includes resistors R1 to R8, operational amplifiers OA1 to PA4, transistors Q1 to Q4, and a power supply E. Power supply E is connected between a node Z0 and a node Z3. Resistors R1 to R3 are connected in series between nodes Z0 and Z3. Resistors R1 to R3 produce intermediate voltages (-V1), (-V2) which are provided by dividing the power supply voltage (-E=-V3) into three.
Resistors R4 to R8 are connected in series between nodes Z0 and Z3. Resistors R4 to R8 produce reference voltages (-VH1, -VL1, and (-VH2, -VL2), for setting acceptable fluctuation values, based on intermediate voltages (-V1), (-V2) as a center. The following expressions (1) to (4) are satisfied between the reference voltages and the intermediate voltages. EQU -VH1=-V1+.DELTA.V (1) EQU -VL1=-V1-.DELTA.V (2) EQU -VH2=-V2+.DELTA.V (3) EQU -VL2=-V2-.DELTA.V (4)
In expressions (1) to (4), .DELTA.V represents an acceptable fluctuation value.
Power supply circuit 920 further includes an operational amplifier OA1 receiving reference voltage (-VH1) at its inversion input terminal ("-") and voltage (-V1) at its non-inversion input terminal ("+"), and a transistor Q2 connected between a node Z1 for outputting voltage (-V1) and node Z3 for outputting a voltage (-V3) and receiving an output of operational amplifier OA1 at its gate. Transistor Q2 is an NMOS transistor. If voltage (-V1) fluctuates and becomes higher than reference voltage (-VH1), transistor Q2 turns on. Thus, fluctuation in the output so that the output is higher than the acceptable value is suppressed.
Power supply circuit 920 further includes an operational amplifier OA2 receiving reference voltage (-VL1, at its inversion input terminal ("-") and voltage (-V1) at its non-inversion input terminal ("+"), and a transistor Q1 connected between node Z1 and node Z0 for outputting a voltage V0 and receiving an output of operational amplifier OA2 at its gate. Transistor Q1 is a PMOS transistor. If voltage (-V1) fluctuates and becomes lower than reference voltage (-VL1), transistor Q1 turns on. Thus, fluctuation in the output so that the output is lower than the acceptable value is suppressed.
Power supply circuit 920 further includes an operational amplifier OA3 receiving reference voltage (-VH2, at its inversion input terminal ("-") and voltage (-V2) at its non-inversion input terminal ("+"), and a transistor Q4 connected between a node Z2 for outputting voltage (-V2) and node Z3 and receiving an output of operational amplifier OA3 at its gate. Transistor Q4 is an NMOS transistor. If voltage (-V2) fluctuates and becomes higher than reference voltage (-VH2, transistor Q4 turns on. Thus, fluctuation in the output so that the output is higher than the acceptable value is suppressed.
Power supply circuit 920 further includes an operational amplifier OA4 receiving reference voltage (-VL2, at its inversion input terminal ("-") and voltage (-V2) at its non-inversion input terminal ("+"), and a transistor Q3 connected between nodes Z2 and Z0 and receiving an output of operational amplifier OA4 at its gate. Transistor Q3 is a PMOS transistor. If voltage (-V2) fluctuates and becomes lower than reference voltage (-VL2), transistor Q3 turns on. Thus, fluctuation in the output so that the output is lower than the acceptable value is suppressed.
In short, fluctuation in each generated voltage (-V1) or (-V2) is limited within the acceptable voltage range 2.times..DELTA.V.
Here, the output impedance of the reference voltage generation circuit (resistors R4 to R8) does not cause any problems even if it is high impedance. This is because operational amplifier outputs are low impedance. Therefore, serial resistors R4 to R8 can have high resistance and current consumption in serial resistors R4 to R8 can be suppressed to be extremely small. Furthermore, the operational amplifiers are dynamically driven only when the outputs fluctuate and become higher or smaller than the acceptable values. Because of the reason as described above, current consumption is extremely small.
However, conventional power supply circuit 920 has the following problems due to variation in the characteristics of circuit components. The conventional problems will be described with reference to FIGS. 15 and 16.
FIG. 16 shows part of a power supply circuit having a similar arrangement to that of power supply circuit 920 described above, and the circuit shown in FIG. 16 is adapted to generate a voltage V4, for example. The power supply circuit shown in FIG. 16 includes a reference voltage generation circuit 94, operational amplifiers OA1, OA2, and an output buffer 5.
Reference voltage generation circuit 94 includes a bleeder resistor R0 to generate reference voltages Va, Vb which define a window width voltage. Output buffer 5 includes transistors Q100, Q200. Transistor Q100 is a PMOS transistor while transistor Q200 is an NMOS transistor. The source of transistor Q100 receives power supply voltage VEE while the source of transistor Q200 receives ground voltage GND. The gate of transistor Q100 receives an output of operational amplifier OA2, and the gate of transistor Q200 receives an output of operational amplifier OA1. The drain of transistor Q100 and the drain of transistor Q200 are both connected to a node for outputting a voltage V4.
Respective non-inversion input terminals (symbol "+") of operational amplifiers OA1, OA2 receive voltage V4. Operational amplifier OA1 receives reference voltage Va at its inversion input terminal (symbol "-"), and operational amplifier OA2 receives reference voltage Vb at its inversion input terminal.
Operational amplifiers OA1, OA2 each have the arrangement shown in FIG. 14. Operational amplifier OA described above having the arrangement shown in FIG. 14 has an offset voltage which is produced by a difference AVth between the threshold voltage of the differential input transistor on the non-inversion input terminal side and a differential input transistor on the inversion input terminal side. For example, the offset voltage is caused by implantation variation when impurities are ion-implanted into a silicon substrate under a region for formation of a transistor gate during the manufacturing process.
In FIG. 16, variation of the offset voltages of operational amplifiers OA1, OA2 in the same direction does not cause any particular problems. However, a total sum of the offset voltages varies in such a direction that reduces window width voltage (Va-Vb) generated by the bleeder resistor in reference voltage generation circuit 94, it causes problems.
Table 1 indicates a case in which the window width voltage was originally set to 100 mV but it became as small as 60 mV because the offset voltages varied in different directions.
TABLE 1 Set Voltage Output Offset Window Window Voltage Voltage Width Operational Va = 1.1 V 1.085 V -l5 mV 60 mV Amplifier OA1 Operational Vb = 1.0 V 1.025 V +25 mV Amplifier OA2
As shown in Table 1, the window width voltage becomes smaller if the offset voltages vary in different directions. If the window width voltage becomes smaller, transistors Q100, Q200 included in output buffer 5 are easily rendered conductive at the same time and a through current is more likely to flow than usual. If the window width voltage becomes much smaller, transistors Q100, Q200 turn on at the same time.
If the through current is produced, the output voltage becomes unstable and actual output voltage V4 becomes lower than an expected value level. When such a power supply circuit is provided in a liquid crystal display device, therefore, problems that a liquid crystal display screen does not start, for example, are caused when power is on.